Semiconductor memory device including clock control circuit and method for operating the same

ABSTRACT

A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority of Korean Patent ApplicationNos. 10-2010-0029592 and 10-2010-0137434, filed on Mar. 31, 2010, andDec. 29, 2010, respectively, which are incorporated herein by referencein their entirety.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to a clock controlcircuit for synchronization control of a semiconductor memory device,and a method for operating a semiconductor memory device including aclock control circuit.

For a high speed operation, a semiconductor memory device is designed toreceive an external clock signal and process commands and data insynchronization with the external clock signal. The external clocksignal inputted to the semiconductor memory device is one of the mainfactors contributing to power dissipation because it is always togglingunder operation conditions of the semiconductor memory device.

FIGS. 1 and 2 are diagrams of a clock control circuit which is used in aknown semiconductor memory device.

As shown, the known clock control circuit includes a first clock buffer14 of FIG. 1 and a second clock buffer 28 of FIG. 2. When a first clockbuffer enable signal CLKBUF1_EN is activated to a logic high level, thefirst clock buffer 14 converts clock signals CLK and CLKB to generatefirst internal clock signals ICLK2F and ICLK2. When a second clockbuffer enable signal CLKBUF2_EN is activated to a logic high level, thesecond clock buffer 28 converts the clock signals CLK and CLKB togenerate second internal clock signals CVR_CLK2 and CVR_CLK1B.

The first clock buffer enable signal CLKBUF1_EN for controlling thefirst clock buffer 14 transitions to a logic high level when a validself-refresh operation signal SREF_FASTB is at a logic high level and aninverted external reset signal RSTB is at a logic high level. Here, thevalid self-refresh operation signal SREF_FASTB is activated in responseto an input timing of an external self-refresh start command signalSREF_CMD, and deactivated in response to an input timing of an externalself-refresh exit command signal EXIT_CMD.

The first clock buffer 14 generates the first internal clock signalsICLK2F and ICLK2 by converting the clock signals CLK and CLKB inresponse to the high-level first clock buffer enable signal CLKBUF1_EN.Except for a self-refresh period, the first internal clock signalsICLK2F and ICLK2 are always toggling and are provided to control aspecific internal block 10 and a self-refresh signal generation unit 20.Therefore, when the semiconductor memory device is operating, the firstclock buffer 14 always consumes an electric current during the togglingoperation. For reference, the specific internal block 10 may include anOn Die Termination (ODT) block and a delay locked loop (DLL) circuit,which are activated in advance prior to a main operation of thesemiconductor memory device.

The clock buffer enable signal CLKBUF2_EN for controlling the secondclock buffer 28 transitions to a logic high level when both an internalself-refresh signal SREF and a power-down signal PWR_DN are at a logiclow level and the inverted external reset signal RSTB is at a logic highlevel. Here, the internal self-refresh signal SREF is activated to alogic high level for a period where a substantial self-refresh operationis performed, and the power-down signal PWR_DN is activated to a logichigh level for a power-down mode of the semiconductor memory device.

The second clock buffer 28 generates the second internal clock signalsCVR_CLK2 and CVR_CLK1B by converting the clock signals CLK and CLKB inresponse to the high-level second clock buffer enable signal CLKBUF2_EN.Except for the self-refresh period, the second internal clock signalsCVR_CLK2 and CVR_CLK1B are always toggling and are provided to control aplurality of internal blocks 30 to 36. Therefore, when the semiconductormemory device is operating, the second clock buffer 28 also alwaysconsumes an electric current during the toggling operation. Forreference, the internal blocks 30 to 36 may include a command decodingunit which is activated for the main operation of the semiconductormemory device.

Hereinafter, referring to FIGS. 1 and 2, an operation of the clockcontrol circuit of a known semiconductor memory device is describedbelow.

FIG. 3 is a timing diagram depicting a case where an internal operationof the semiconductor memory device is in an idle state after aself-refresh control operation is completed.

Referring to FIG. 3, when the self-refresh start command signal SREF_CMDis input, a clock enable signal CKE and the idle signal IDLE aredeactivated to a logic low level, the valid self-refresh operationsignal SREF_FASTB is activated to a logic low level, and the internalself-refresh signal SREF is activated to a logic high level. In responseto the low-level valid self-refresh operation signal SREF_FASTB, thefirst clock buffer enable signal CLKBUF1_EN is deactivated to a logiclow level, and thus the first clock buffer 14 stops a toggling of thefirst internal clock signal ICLK2. Meanwhile, in response to thehigh-level internal self-refresh signal SREF, the second clock bufferenable signal CLKBUF2_EN is deactivated to a logic low level, and thusthe second clock buffer 28 stops a toggling of the second internal clocksignal CVR_CLK2.

After an internal self-refresh operation is performed, the self-refreshexit command signal EXIT_CMD is input. In response to the self-refreshexit command signal EXIT_CMD, the clock enable signal CKE is activatedto a logic high level and the valid self-refresh operation signalSREF_FASTB is deactivated to a logic high level. At this time, the idlesignal IDLE becomes a logic high level since there are no low-activebanks among internal banks of the semiconductor memory device. Inresponse to the high-level valid self-refresh operation signalSREF_FASTB, the first clock buffer enable signal CLKBUF1_EN is activatedto a logic high level, and thus the first clock buffer 14 startstoggling of the first internal clock signal ICLK2. The self-refreshsignal generation unit 20 deactivates the internal self-refresh signalSREF to a logic low level in response to the toggling of the firstinternal clock signal ICLK2, and thus, the second clock buffer enablesignal CLKBUF2_EN is activated to a logic high level. Accordingly, thesecond clock buffer 28 starts toggling of the second internal clocksignal CVR_CLK2.

FIG. 4 is a timing diagram depicting a case where the internal operationof the semiconductor memory device is not in an idle state after aself-refresh control operation is completed.

Referring to FIG. 4, when the self-refresh start command signal SREF_CMDis input, the first clock buffer 14 stops a toggling of the firstinternal clock signal ICLK2 and the second clock buffer 28 stops atoggling of the second internal clock signal CVR_CLK2, as described inFIG. 3.

After the internal self-refresh operation is performed, the self-refreshexit command signal EXIT_CMD is input. In response to the self-refreshexit command signal EXIT_CMD, the clock enable signal CKE is activatedto a logic high level and the valid self-refresh operation signalSREF_FASTB is deactivated to a logic high level. At this time, the idlesignal IDLE maintains a logic low level since at least one bank isactivated. In response to the high-level valid self-refresh operationsignal SREF_FASTB, the first clock buffer enable signal CLKBUF1_EN isactivated to a logic high level, and thus the first clock buffer 14starts toggling of the first internal clock signal ICLK2. However, theself-refresh signal generation unit 20 maintains the internalself-refresh signal SREF at a logic high level until the idle signalIDLE is activated to a logic high level. When the idle signal IDLEtransitions to a logic high level, the self-refresh signal generationunit 20 deactivates the internal self-refresh signal SREF to a logic lowlevel in response to the toggling of the first internal clock signalICLK2. As a result, the second clock buffer enable signal CLKBUF2_EN isactivated to a logic high level, and the second clock buffer 28 startstoggling of the second internal clock signal CVR_CLK2.

Such a conventional clock control circuit requires two clock buffers inorder to generate the necessary clock signals. Therefore, the two clockbuffers must maintain the toggling operation state in almost all states,causing an undesirable current consumption.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to asemiconductor memory device including a clock control circuit whichcontrols clock signals to thereby prevent power consumption caused bythe toggling of clock signals.

Exemplary embodiments of the present invention are also directed to amethod for operating a semiconductor memory device including a clockcontrol circuit which controls clock signals to thereby prevent powerconsumption caused by the toggling of clock signals.

In accordance with an exemplary embodiment of the present invention, asemiconductor memory device includes a first clock buffer configured totoggle a first clock signal when a self-refresh exit command signal isinputted during a self-refresh operation; and a second clock bufferconfigured to toggle a second clock signal when the self-refreshoperation is finished, the second clock being provided to internalcircuits.

In accordance with another exemplary embodiment of the presentinvention, a semiconductor memory device includes a first clock bufferconfigured to toggle a first clock signal from an input timing of aself-refresh exit command signal up to a timing when an internalself-refresh operation, which is controlled according to theself-refresh exit command signal, is finished, a self-refresh signalgeneration unit configured to generate a self-refresh signal which isactivated in response to a self-refresh start command signal, anddeactivated in response to the first clock signal, a second clock bufferconfigured to toggle a second clock signal in response to theself-refresh signal, and a plurality of internal circuits configured touse the second clock signal.

In accordance with yet another exemplary embodiment of the presentinvention, a semiconductor memory device includes a first enable controlunit configured to generate a first clock enable signal which isactivated from an input timing of a self-refresh exit command signaluntil an internal self-refresh operation is finished, a first clockbuffer configured to toggle a first clock signal in response to thefirst clock enable signal, the first clock signal being used in aself-refresh control circuit, a second enable control unit configured togenerate a second clock enable signal which is activated after theinternal self-refresh operation is finished, and a second clock bufferconfigured to toggle a second clock signal in response to the secondclock enable signal, the second clock signal being used in a pluralityof internal circuits.

In accordance with still another exemplary embodiment of the presentinvention, a method for operating a semiconductor memory device includesgenerating a first clock signal toggling from an input timing of aself-refresh exit command signal up to a timing when an internalself-refresh operation is finished, generating a self-refresh signalwhich is activated in response to a self-refresh start command signal,and deactivated in response to the first clock signal, and generating asecond clock signal toggling in response to the self-refresh signal, thesecond clock signal being used in a plurality of internal circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are diagrams of a known clock control circuit.

FIG. 3 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is in an idle state after aself-refresh control operation is completed.

FIG. 4 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is not in an idle state after aself-refresh control operation is completed.

FIGS. 5 and 6 are diagrams of a clock control circuit in accordance withan exemplary embodiment of the present invention.

FIG. 7 is a diagram of a self-refresh signal generation unit inaccordance with an exemplary embodiment of the present invention.

FIG. 8 is a circuit diagram of a first signal output unit illustrated inFIG. 7.

FIG. 9 is a circuit diagram of a second signal output unit illustratedin FIG. 7.

FIG. 10 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is in an idle state after aself-refresh control operation is completed, in accordance with anexemplary embodiment of the present invention.

FIG. 11 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is not in an idle state after aself-refresh control operation is completed, in accordance with anexemplary embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

FIGS. 5 and 6 are diagrams of a clock control circuit in accordance withan exemplary embodiment of the present invention.

As shown, the clock control circuit in accordance with an exemplaryembodiment of the present invention includes a first clock buffer 66 ofFIG. 5 and a second clock buffer 78 of FIG. 6. When a first clock bufferenable signal CLKBUF1_EN becomes a logic high level, the first clockbuffer 66 converts clock signals CLK and CLKB to generate first internalclock signals ICLK2 and ICLK2F. Further, when a second clock bufferenable signal CLKBUF2_EN becomes a logic high level, the second clockbuffer 78 converts the clock signals CLK and CLKB to generate secondinternal clock signals CVR_CLK2 and CVR_CLK1B.

The first clock buffer 66 is enabled when an internal self-refreshsignal SREF, a valid self-refresh operation signal SREF_FASTB, and aninverted external reset signal RSTB are at a logic high level. Here, thevalid self-refresh operation signal SREF_FASTB is activated in responseto an input timing of an external self-refresh start command signalSREF_CMD, and deactivated in response to an input timing of an externalself-refresh exit command signal EXIT_CMD.

To this end, a first enable control unit 60 comprises an AND gate 64 andis configured to generate the first clock buffer enable signalCLKBUF1_EN based on the internal self-refresh signal SREF, the validself-refresh operation signal SREF_FASTB, and the inverted externalreset signal RSTB.

The first clock buffer 66 generates the first internal clock signalsICLK2F and ICLK2 by converting the clock signals CLK and CLKB inresponse to the high-level first clock buffer enable signal CLKBUF1_EN.In response to a toggling of the first internal clock signals ICLK2F andICLK2, a self-refresh signal generation unit 69 deactivates the internalself-refresh signal SREF to a logic low level. Further, in response tothe low-level internal self-refresh signal SREF, the first clock buffer66 is disabled again. Accordingly, the first clock buffer 66 iscontrolled to be activated/deactivated in response to the first clockbuffer enable signal CLKBUF1_EN output from the first enable controlunit 60, and outputs the first internal clock signal ICLK2 via aninverter 68.

Meanwhile, the second clock buffer 78 is enabled when the invertedexternal reset signal RSTB and the internal self-refresh signal SREF areat a logic high level.

To this end, a second enable control unit 70 comprises an inverter 72and an AND gate 76 and is configured to generate the second clock bufferenable signal CLKBUF2_EN based on the inverted external reset signalRSTB and an inversion of the internal self-refresh signal SREF. Theinverter 72 inverts the internal self-refresh signal SREF, and the ANDgate 76 performs an AND operation on an output of the inverter 72 andthe inverted external reset signal RSTB. Accordingly, the second clockbuffer 78 generates the second internal clock signals CVR_CLK2 andCVR_CLK1B by converting the clock signals CLK and CLKB in response tothe high-level second clock buffer enable signal CLKBUF2_EN.

In accordance with an exemplary embodiment of the present invention,only the self-refresh signal generation unit 69 is configured to use thefirst internal clock signals ICLK2F and ICLK2, while all internalcircuits 80 to 88 are configured to use the second internal clocksignals CVR_CLK2 and CVR_CLK1B. That is, the clock control circuitcontrols the first and second clock buffers 66 and 78 to toggle thefirst internal clock signals ICLK2F and ICLK2 at different times thanthe second internal clock signals CVR_CLK2 and CVR_CLK1B. Here, mostinternal circuits 80 to 88 use the second internal clock signalsCVR_CLK2 and CVR_CLK1B, which continuously toggle except during theself-refresh period. Therefore, in accordance with an exemplaryembodiment of the present invention, power consumption occurring due toan overlap of toggling operations of two clock signals may be reduced.

FIG. 7 is a diagram of the self-refresh signal generation unit 69 inaccordance with an exemplary embodiment of the present invention. FIGS.8 and 9 are circuit diagrams of a first signal output unit 40 and asecond signal output unit 42 illustrated in FIG. 7, respectively. Here,the self-refresh signal generation unit 69 generates the internalself-refresh signal SREF to control operations of the first and secondclock buffers 66 and 78 and to control an internal self-refreshoperation.

Referring to FIG. 7, the self-refresh signal generation unit 69comprises the first and second signal output units 40 and 42. The firstsignal output unit 40 generates a self-refresh disable timingdetermination signal SREFEXTB, which determines a timing to disable theinternal self-refresh operation, based on an idle signal IDLE, aninverted external reset signal RSTB, a self-refresh control signalSREFD, and the first internal clock signal ICLK2. The second signaloutput unit 42 generates the internal self-refresh signal SREF inresponse to the self-refresh disable timing determination signalSREFEXTB and the external self-refresh start command signal SREF_CMD.

In detail, the first signal output unit 40 activates and outputs theself-refresh disable timing determination signal SREFEXTB at a logic lowlevel when the first internal clock signal ICLK2 is toggling and theidle signal IDLE, the inverted external reset signal RSTB, and theself-refresh control signal SREFD are all at a logic high level. Here,the idle signal IDLE is activated to a logic high level when there areno low-active banks among internal banks of the semiconductor memorydevice.

Referring to FIG. 8, the first signal output unit 40 comprises first tothird logic gates 44, 46, and 48. The first logic gate 44 performs anAND operation on the first internal clock signal ICLK2 and theself-refresh control signal SREFD. The second logic gate 46 performs aNAND operation on an output of the first logic gate 44 and the idlesignal IDLE. The third logic gate 48 performs an AND operation on theinverted external reset signal RSTB and an output of the second logicgate 46 to output the self-refresh disable timing determination signalSREFEXTB.

The second signal output unit 42 activates the internal self-refreshsignal SREF to a logic high level in response to the externalself-refresh start command signal SREF_CMD, and deactivates the internalself-refresh signal SREF to a logic low level in response to theself-refresh disable timing determination signal SREFEXTB.

Referring to FIG. 9, the second signal output unit 42 comprises a latchunit 52, an inverter chain 54, and a delay unit 56. The latch unit 52comprises two NAND gates to be set/reset in response to the externalself-refresh start command signal SREF_CMD and the self-refresh disabletiming determination signal SREFEXTB. The inverter chain 54 inverts anddelays an output of the latch unit 52 to output the internalself-refresh signal SREF. The delay unit 56 delays the internalself-refresh signal SREF to output the self-refresh control signalSREFD.

Hereinafter, referring to FIGS. 5 to 9, an operation of the clockcontrol circuit of the semiconductor memory device in accordance with anexemplary embodiment of the present invention will be described below.

FIG. 10 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is in an idle state after aself-refresh control operation is completed, in accordance with anexemplary embodiment of the present invention.

Referring to FIG. 10, before the self-refresh start command signalSREF_CMD is input, the internal self-refresh signal SREF is deactivatedto a logic low level. The first enable control unit 60 deactivates thefirst clock buffer enable signal CLKBUF1_EN to a logic low level, andthus the first clock buffer 66 is deactivated so as to stop a togglingof the first internal clock signal ICLK2. Further, since the internalself-refresh signal SREF is deactivated to a logic low level, the secondenable control unit 70 activates the second clock buffer enable signalCLKBUF2_EN to a logic high level, and thus the second clock buffer 78 isactivated to output the second internal clock signal CVR_CLK2 so that ittoggles.

When the self-refresh start command signal SREF_CMD is input, a clockenable signal CKE and the idle signal IDLE are deactivated to a logiclow level, the valid self-refresh operation signal SREF_FASTB isactivated to a logic low level, and the internal self-refresh signalSREF is activated to a logic high level. At this time, since the secondclock buffer enable signal CLKBUF2_EN is deactivated to a logic lowlevel in response to the high-level internal self-refresh signal SREF,the second clock buffer 78 stops a toggling of the second internal clocksignal CVR_CLK2. On the other hand, since the valid self-refreshoperation signal SREF_FASTB is a logic low level in spite of thehigh-level internal self-refresh signal SREF, the first clock buffer 66maintains a deactivation state. As a result, the first internal clocksignal ICLK2 still does not toggle.

After an internal self-refresh operation is performed, the self-refreshexit command signal EXIT_CMD is input. In response to the self-refreshexit command signal EXIT_CMD, the clock enable signal CKE is activatedto a logic high level and the valid self-refresh operation signalSREF_FASTB is deactivated to a logic high level. At this time, the idlesignal IDLE becomes a logic high level since there are no low-activebanks among internal banks of the semiconductor memory device. The firstenable control unit 60 activates the first clock buffer enable signalCLKBUF1_EN to a logic high level in response to the high-level validself-refresh operation signal SREF_FASTB and the high-level internalself-refresh signal SREF. As a result, the first clock buffer 66 isactivated to start a toggling of the first internal clock signal ICLK2.Accordingly, the first signal output unit 40 activates the self-refreshdisable timing determination signal SREFEXTB to a logic low level, andthe second signal output unit 42 deactivates the internal self-refreshsignal SREF to a logic low level.

In response to the low-level internal self-refresh signal SREF, thefirst clock buffer enable signal CLKBUF1_EN is deactivated to a logiclow level while the second clock buffer enable signal CLKBUF2_EN isactivated to a logic high level. As a result, the first clock buffer 66stops the toggling of the first internal clock signal ICLK2, while thesecond clock buffer 78 starts a toggling of the second internal clocksignal CVR_CLK2.

FIG. 11 is a timing diagram depicting a case where an internal operationof a semiconductor memory device is not in an idle state after aself-refresh control operation is completed, in accordance with anexemplary embodiment of the present invention.

Referring to FIG. 11, before the self-refresh start command signalSREF_CMD is input, in response to the low-level internal self-refreshsignal SREF, the first clock buffer 66 is deactivated so as to stop atoggling of the first internal clock signal ICLK2. However, the secondclock buffer 78 is activated to output the second internal clock signalCVR_CLK2 so that it toggles.

When the self-refresh start command signal SREF_CMD is input, the clockenable signal CKE and the idle signal IDLE are deactivated to a logiclow level, the valid self-refresh operation signal SREF_FASTB isactivated to a logic low level, and the internal self-refresh signalSREF is activated to a logic high level. At this time, since the secondclock buffer enable signal CLKBUF2_EN is deactivated in response to thehigh-level internal self-refresh signal SREF, the second clock buffer 78stops the toggling of the second internal clock signal CVR_CLK2. On theother hand, since the valid self-refresh operation signal SREF_FASTB isa logic low level in spite of the high-level internal self-refreshsignal SREF, the first clock buffer 66 maintains a deactivation state.As a result, the first internal clock signal ICLK2 still does nottoggle.

After an internal self-refresh operation is performed, the self-refreshexit command signal EXIT_CMD is input. In response to the self-refreshexit command signal EXIT_CMD, the clock enable signal CKE is activatedto a logic high level and the valid self-refresh operation signalSREF_FASTB is deactivated to a logic high level. At this time, the idlesignal IDLE maintains a logic low level since at least one bank isactivated.

The first enable control unit 60 activates the first clock buffer enablesignal CLKBUF1_EN to a logic high level in response to the high-levelvalid self-refresh operation signal SREF_FASTB and the high-levelinternal self-refresh signal SREF. As a result, the first clock buffer66 is activated to start a toggling of the first internal clock signalICLK2. Since the idle signal IDLE maintains a logic low state, the firstsignal output unit 40 deactivates the self-refresh disable timingdetermination signal SREFEXTB to a logic high level regardless of thetoggling of the first internal clock signal ICLK2. Thus, the secondsignal output unit 42 maintains the internal self-refresh signal SREF ata logic high level.

When the idle signal IDLE becomes a logic high level since there are nolow-active banks among internal banks of the semiconductor memorydevice, the first signal output unit 40 activates the self-refreshdisable timing determination signal SREFEXTB to a logic low level inresponse to the toggling of the first internal clock signal ICLK2. Thesecond signal output unit 42 deactivates the internal self-refreshsignal SREF to a logic low level in response to the self-refresh disabletiming determination signal SREFEXTB.

In response to the low-level internal self-refresh signal SREF, thefirst clock buffer enable signal CLKBUF1_EN is deactivated to a logiclow level while the second clock buffer enable signal CLKBUF2_EN isactivated to a logic high level. As a result, the first clock buffer 66stops the toggling of the first internal clock signal ICLK2 while thesecond clock buffer 78 starts a toggling of the second internal clocksignal CVR_CLK2.

In accordance with the exemplary embodiments of the present invention, aclock control circuit includes a first clock buffer which controls atoggling of a first clock signal during only a self-refresh exitoperation, and a second clock buffer which controls toggling of a secondclock signal during the other operations. Using these clock buffers, theclock control circuit controls toggling of the first and second clocksignals so that they are not toggled at the same time (i.e., so thattoggling durations do not overlap). Therefore, power consumptionoccurring during an operation of toggling the clock signals may bereduced.

The embodiments of the present invention can be applied to circuits anddevices which achieve power reduction by appropriately controlling theoperation of toggling the clock signals.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A clock control circuit comprising: a first clockbuffer configured to toggle a first clock signal when a self-refreshexit command signal is inputted during a self-refresh operation; asecond clock buffer configured to toggle a second clock signal when theself-refresh operation is finished, the second clock being provided tointernal circuits; a first signal output unit configured to generate aself-refresh disable timing determination signal; and a second signaloutput unit configured to generate the self-refresh signal in responseto the self-refresh disable timing determination signal.
 2. The clockcontrol circuit of claim 1, wherein the first clock buffer starts atoggling of the first clock signal when the self-refresh exit commandsignal is inputted, and stops the toggling of the first clock signalwhen the self-refresh operation is finished in response to theself-refresh exit command signal.
 3. The clock control circuit of claim1, wherein the second clock buffer starts a toggling of the second clocksignal in response to a signal generated based on the first clock signaloutputted from the first clock buffer.
 4. The clock control circuit ofclaim 1, further comprising: a first enable control unit configured togenerate a first clock buffer enable signal for controlling the firstclock buffer based on the self-refresh exit command signal and aself-refresh signal; and a second enable control unit configured togenerate a second clock buffer enable signal for controlling the secondclock buffer based on an inverted signal of the self-refresh signal. 5.A semiconductor memory device comprising: a first clock bufferconfigured to toggle a first clock signal from an input timing of aself-refresh exit command signal up to a timing when an internalself-refresh operation, which is controlled according to theself-refresh exit command signal, is finished; a self-refresh signalgeneration unit configured to generate a self-refresh signal which isactivated in response to a self-refresh start command signal, anddeactivated in response to the first clock signal; a second clock bufferconfigured to toggle a second clock signal in response to theself-refresh signal; and a plurality of internal circuits configured touse the second clock signal.
 6. The semiconductor memory device of claim5, wherein the second clock buffer toggles the second clock signal inresponse to a deactivation of the self-refresh signal.
 7. Thesemiconductor memory device of claim 5, wherein the self-refresh signalgeneration unit comprises: a first signal output unit configured togenerate a self-refresh disable timing determination signal, whichdetermines a timing to finish the internal self-refresh operation, basedon an idle signal, a delay signal of the self-refresh signal, and thefirst clock signal; and a second signal output unit configured togenerate the self-refresh signal in response to the self-refresh disabletiming determination signal and the self-refresh start command signal.8. The semiconductor memory device of claim 7, wherein the first signaloutput unit activates the self-refresh disable timing determinationsignal when the first clock signal is toggling and the idle signal andthe delay signal of the self-refresh signal are activated, the idlesignal being activated when there are no low-active banks among internalbanks of the semiconductor memory device.
 9. The semiconductor memorydevice of claim 7, wherein the first signal output unit comprises: afirst logic gate configured to perform an AND operation on the firstclock signal and the delay signal of the self-refresh signal; and asecond logic gate configured to perform a NAND operation on an output ofthe first logic gate and the idle signal to output the self-refreshdisable timing determination signal.
 10. The semiconductor memory deviceof claim 7, wherein the second signal output unit activates theself-refresh signal in response to the self-refresh start commandsignal, and deactivates the self-refresh signal in response to theself-refresh disable timing determination signal.
 11. The semiconductormemory device of claim 7, wherein the second signal output unitcomprises: an RS latch unit configured to be set/reset in response tothe self-refresh start command signal and the self-refresh disabletiming determination signal; an inverter chain configured to invert anddelay an output of the RS latch unit to output the self-refresh signal;and a delay unit configured to delay the self-refresh signal to outputthe delay signal of the self-refresh signal.
 12. A semiconductor memorydevice comprising: a first enable control unit configured to generate afirst clock enable signal which is activated from an input timing of aself-refresh exit command signal until an internal self-refreshoperation is finished; a first clock buffer configured to toggle a firstclock signal in response to the first clock enable signal, the firstclock signal being used in a self-refresh control circuit; a secondenable control unit configured to generate a second clock enable signalwhich is activated after the internal self-refresh operation isfinished; and a second clock buffer configured to toggle a second clocksignal in response to the second clock enable signal, the second clocksignal being used in a plurality of internal circuits.
 13. Thesemiconductor memory device of claim 12, wherein the second enablecontrol unit generates the second clock enable signal in response to aself-refresh signal generated by the self-refresh control circuit. 14.The semiconductor memory device of claim 13, wherein the self-refreshcontrol circuit comprises: a first signal output unit configured togenerate a self-refresh disable timing determination signal, whichdetermines a timing to finish the internal self-refresh operation, basedon a delay signal of the self-refresh signal and the first clock signal;and a second signal output unit configured to generate the self-refreshsignal in response to the self-refresh disable timing determinationsignal and the self-refresh start command signal.
 15. A method foroperating a semiconductor memory device, the method comprising:generating a first clock signal toggling from an input timing of aself-refresh exit command signal up to a timing when an internalself-refresh operation is finished; generating a self-refresh signalwhich is activated in response to a self-refresh start command signal,and deactivated in response to the first clock signal; and generating asecond clock signal toggling in response to the self-refresh signal, thesecond clock signal being used in a plurality of internal circuits. 16.The method of claim 15, wherein the generating of the second clocksignal comprises toggling the second clock signal in response to adeactivation of the self-refresh signal.
 17. The method of claim 15,wherein the generating of the self-refresh signal comprises: generatinga self-refresh disable timing determination signal, which determines atiming to finish the internal self-refresh operation, based on an idlesignal, a delay signal of the self-refresh signal, and the first clocksignal; and generating the self-refresh signal in response to theself-refresh disable timing determination signal and the self-refreshstart command signal.
 18. The method of claim 17, wherein the generatingof the self-refresh disable timing determination signal comprises:activating the self-refresh disable timing determination signal when thefirst clock signal is toggling and the idle signal and the delay signalof the self-refresh signal are activated, the idle signal beingactivated when there are no low-active banks among internal banks of thesemiconductor memory device.
 19. The method of claim 17, wherein thegenerating of the self-refresh signal comprises: activating theself-refresh signal in response to the self-refresh start commandsignal, and deactivating the self-refresh signal in response to theself-refresh disable timing determination signal.